The Noisy Road Ahead
In order to increase device speed and reduce cost, semiconductor manufacturers continue to aggressively scale their devices and move to new materials. The International Technology Roadmap for Semiconductors posits continued reductions in signal size and strength: operating voltage, MOS threshold voltage and allowable Vt shift. As your signals and measurement tolerances become ever smaller, signal-to-noise ratio degrades, and "noise headroom" is rapidly becoming a thing of the past.
PureLine ensures confidence in your test data from process development through characterization and modeling to long term reliability and failure analysis test. Cascade Microtech probing systems with PureLine technology will keep you on the road and ahead of the curve.
|MOS DC Characterization|
With reduced scaling, the MOS device operating range is narrowing and threshold voltage continues to fall. In the future, applied gate voltage step increments for Vt and gm measurement may be reduced to account for the narrower operating range. But with ever-lower voltage step increments the measurement becomes much more susceptible to perturbations due to background transmissions and noise – especially the derivative gm curve.
PureLine systems are specifically designed to minimize transmission of electromagnetic interference to the semiconductor device. This means reduced risk of spurious voltages appearing at the device terminals – resulting in better measurement repeatability and accuracy.
With ultra thin gate oxides and lower operating range, the AC stimulus voltage used for capacitance measurement is decreasing. Further, higher frequencies are now often used to better isolate capacitance from oxide tunneling currents – for high frequency the Short and Load calibration becomes essential. Reliable Short and Load calibrations at low stimulus levels depend on a very low background voltage noise content. A lower noise environment means fewer LCR meter “bridge unbalanced” errors.
By reducing background transmissions and noise, PureLine systems deliver very low levels of substrate voltage noise – even when a thermal controller is used. Short and Load calibrations at lower stimulus levels are no longer at risk.
|1/f - Flicker Noise|
With increased usage of CMOS technology for wireless applications, flicker noise (1/f) has become a more critical parameter and its measurement more widespread. But background transmissions or noise can easily mask the measured noise.
PureLine systems were designed with flicker noise measurement in mind. In addition to improved RFI immunity, other engineered enhancements reduce conducted and locally-generated emissions.
|Reliability - TDDB|
Precision stress voltage control is needed for accurate device time-to-breakdown (TBD) and lifetime projection. But reduced scaling means lower applied stress voltages. This places the TBD measurement at greater risk from fixed levels of spurious voltage transients that may ride on the stressing voltage.
Through effective RFI shielding and by reducing conducted emissions, PureLine technology controls substrate noise for cleaner and better controlled TBD stress voltage.