Cascade Microtech's Thin Film Technology

Each Pyramid Probe design is customized for individual or multi-die pad configurations and is designed to meet your electrical specifications.

Pyramid Probe membrane layer with logic circuitsProbe tips, as well as the metal layers and vias between layers, are photolithographically defined and processed using methods similar to semiconductor manufacturing.

Layers of polyimide on the top and bottom of the membrane encapsulate the conductors so that the only exposed contacts are the probe tips. Non-oxidizing nickel alloy probe tips are plated and connected to the different conductor layers through vias.

The first metal layer is typically the ground plane, which can be split to isolate grounds if needed. The second layer is used to route the signal conductors. Photo-processed vias can connect the two layers.

High-density routing to multiple rows of periphery pads, arrays of bond pads, or solder bumps is possible using the two metal layers.

Pyramid Probe membrane layer with capacitorsWith a wide solid ground and a narrower conductor trace, 50-ohm controlled impedances can be maintained from the bond pad to the test equipment providing the degree of signal integrity required for full functional test.

Any combination of RF, DC, power, and ground-pad layouts can be probed as the membrane layout is specifically designed to fit each device’s pad geometry.

Typically, probe designers work from a table listing x-y locations of the pads. Probe tips can then be placed in precise locations on the bond pads to minimize pad-to-pad misalignment. This is beneficial to operators because there is no longer the issue of probe-to-pad alignment on an individual die or array of devices.